The PCIExpress bus is an improved version of the PCI bus. It maintains the PCI software usage model and uses a high-speed (2.5Gb/s) serial bus with multiple lanes to replace the physical bus. It maintains compatibility with the PCI addressing mode (load-store architecture with a single-level address space), thus ensuring that all existing applications and driver operations do not need to be changed.
PCIExpress configuration uses the standard mechanism defined in the PCI Plug and Play standard. The software layer issues read and write requests and transmits them through the processing layer to the I/O device using a packet-based, segmented transfer protocol. The link layer adds sequence numbers and cyclic redundancy checks (CRC) to these packets to create a highly reliable data transmission mechanism.
The basic physical layer includes two simplex channels, namely a transmit pair and a receive pair. This transmit pair and receive pair together are called a channel. The initial speed of 2.5Gb/s provides approximately 250MB/s standard bandwidth in each direction on each PCIExpress channel. Once the protocol headers are taken into account, approximately 200MB/s of this is used by the device to transfer data.
Based on the advancement of PCIExpress bus, data acquisition cards using PCIExpress bus will be the general trend, especially high-speed acquisition cards. In terms of speed, the single-direction transmission and reception rate of PCIe1.0 is 250MB/s, PCIe2.0 is 500MB/s, and PCIe 3.0 is 800MB/s. If it is a PCIe high-speed data acquisition card of PCIeX82.0, the actual bus transmission rate will reach more than 3GB/s.
